1. Field of the invention
The present invention concerns a display control unit for a CRT display device of office computers, personal computers, word processors, DPS (data processing systems) or like other various data processing devices having display terminals.
More specifically, it relates to a display control unit for displaying video data sent from at least two independent video information sources on a screen of a single CRT display device, and particularly, it relates to a display control unit for combining video data transmitted from a plurality of subsystems each controlled by its inherent pixel clocks, synchronizing signals, etc. with that of a main system so that they can be seen simultaneously on one identical screen, thereby effectively utilizing video information sources, as well as improving operability.
2. Description of the prior art
There has been known an image display system in which video information sources controlled by their respective pixel clocks, sync signals, etc. frequencies of which differ with respect to each other, are connected together, and their video data are displayed on a single CRT display device.
In the following description, an image display system having one CRT display device controlled by a sync signal having an inherent frequency is referred to as a main system, while image display systems other than the above-mentioned main system are referred to as subsystems.
The main system has a function of preparing its own video data and mixing the same with video data transmitted from subsystems so that a user can display them on one identical screen.
For displaying video data of main system and those of at least two subsystems on one identical CRT display screen, two methods have been known so far in the computer field.
In the first method, each of the main system and subsystems comprises a CPU, a video buffer memory for storing the video data outputted from the CPU, a CRT controller for reading out the video data from the video buffer memory and converting the data into serial signals and a CRT display device for receiving the serial signals from the CRT controller and displaying the signals.
For transferring the video data of the subsystems to the main system, CPUs of the main system and the subsystems are connected by way of an interface. Since the video data of the subsystem stored in the video buffer memory of the subsystem is transferred by way of the CPUs of the subsystem and the main system to the buffer memory of the main system in the first method, it has a disadvantage that it takes much time to transfer the video data.
In the second method, the CRT controller of the main system and the buffer memory of the subsystem are connected so that the CRT controller of the main system can directly read out the video data from the buffer memory of the subsystem.
However, respective subsystems are generally manufactured by different manufacturers.
In view of the above, since sync signal, etc. are different, it is difficult in many cases for the CRT controller of the main system to directly access the video buffer memories of the subsystems.
Accordingly, an interface similar to that of the first method is required in most cases so that no remarkable effect can be expected.
In this way, the prior methods described above involve drawbacks that they require a complicated interface or require much processing time for displaying the video data of the subsystems at the CRT display device of the main system, etc.
The present invention has been made in view of the foregoings and the object thereof is to provide a display control unit for mixing the video data of subsystems having different sync signals and pixel clocks with the video data of the main system and displaying the mixed data on a screen of a CRT display device of the main system, which does not require to modify the hard wares of the subsystems or to move the video data in the video buffer memory of the subsystem to the video buffer memory of the main system, to shorten transferring time of the video data of the subsystems.
The foregoing object of the present invention can be attained by a display control unit for combining first video signal transmitted from a first video information source which is controlled by a first pixel clock and a first synchronizing signal with second video signal transmitted from a second video information source which is controlled by a second pixel clock and a second synchronizing signal so that the first and the second video signals can be displayed on a CRT display device which is controlled by the first pixel clock and the first synchronizing signal, said unit comprising;
a video buffer means to be connected to said second video information source for storing said second video signal, PA1 third pixel clock generating means to be connected to said first information source for generating a third pixel clock in accordance with said first synchronizing signal and said second pixel clock, and PA1 video signal selecting means to be connected to said first video information source, and connected to said buffer means and said third pixel clock generating means for selectively outputting said first video signal sent from said first video information source and said second video signal transferred from said video buffer means at a rate of said third pixel clock.
In a case where two video information sources are independent with each other, there often occurs such a case that at the moment when the main system displays a certain pixel on a certain scanning line, a subsystem displays a different pixel on a different scanning line.
In the present invention, video information sources independent with each other and also different with respect to their sync signals, etc. can be combined and displayed on one identical screen by the following idea.
In the device according to the present invention, memories called video buffer are used for storing the video data of each frame of the subsystem. While the video data of a certain frame is being stored, the video data of another frame stored in the video buffer is taken out and displayed on the screen.
In other words, the video buffer has a dual port structure in which any video data sent out from the subsystem is once stored in the video buffer, and simultaneously, other video data is read out from the video buffer at proper timings to be displayed on the CRT screen of the main system.
In the display control unit according to the present invention, the videobbuffer having such a dual port structure is used.